The present invention is related to the field of semiconductor fabrication and more particularly to a method and structure for reducing soft error rate in a semiconductor circuit.
Semiconductor memory products are susceptible to a data loss phenomenon generally referred to as soft errors. Soft errors in semiconductor products may result from environmental radiation that alters the amount of charge stored on a semiconductor circuit such as a static random access memory (SRAM) or dynamic random access memory (DRAM) device. In many integrated circuits including SRAMs and DRAMs, the logical state of the integrated circuit is dependent upon an extremely small amount of stored charge. Environmental particle radiation originating from a variety of sources can alter the amount of charge stored in a cell or element of a memory device. It will be appreciated that the soft error rate varies with the amount of charge stored on a storage node of the memory device. As the power supply voltage and the cell size of memory devices decrease, the amount of charge stored decreases accordingly thereby increasing the probability of a soft error event. Therefore, it would be highly desirable to implement a process and device that could substantially reduce the soft error rate without significantly increasing the cost or complexity of the process.